Cost Management Against Requirements for the Generation of a NoC

ABSTRACT

Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

CROSS REFERENCE TO RELATED APPLICATIONS

This regular U.S. patent application is a Continuation application based on U.S. patent application Ser. No. 15/885,297, filed on Jan. 31, 2018, which claims the benefit of priority under 35 U.S.C. 119 from provisional U.S. patent application No. 62/453,431, filed on Feb. 1, 2017, the entire disclosure of which is incorporated by reference herein.

BACKGROUND Technical Field

Methods and example implementations described herein are directed to interconnect architecture, and more specifically, to generation of a Network on Chip (NoC) based on requirements and cost management.

Related Art

The number of components on a chip is rapidly growing due to increasing levels of integration, system complexity and shrinking transistor geometry. Complex System-on-Chips (SoCs) may involve a variety of components e.g., processor cores, DSPs, hardware accelerators, memory and I/O, while Chip Multi-Processors (CMPs) may involve a large number of homogenous processor cores, memory and I/O subsystems. In both SoC and CMP systems, the on-chip interconnect plays a role in providing high-performance communication between the various components. Due to scalability limitations of traditional buses and crossbar based interconnects, Network-on-Chip (NoC) has emerged as a paradigm to interconnect a large number of components on the chip. NoC is a global shared communication infrastructure made up of several routing nodes interconnected with each other using point-to-point physical links.

Messages are injected by the source and are routed from the source node to the destination over multiple intermediate nodes and physical links. The destination node then ejects the message and provides the message to the destination. For the remainder of this application, the terms ‘components’, ‘blocks’, ‘hosts’ or ‘cores’ will be used interchangeably to refer to the various system components which are interconnected using a NoC. Terms ‘routers’ and ‘nodes’ will also be used interchangeably. Without loss of generalization, the system with multiple interconnected components will itself be referred to as a ‘multi-core system’.

There are several topologies in which the routers can connect to one another to create the system network. Bi-directional rings (as shown in FIG. 1(a)), 2-D (two dimensional) mesh (as shown in FIG. 1(b)) and 2-D Taurus (as shown in FIG. 1(c)) are examples of topologies in the related art. Mesh and Taurus can also be extended to 2.5-D (two and half dimensional) or 3-D (three dimensional) organizations. FIG. 1(d) shows a 3D mesh NoC, where there are three layers of 3×3 2D mesh NoC shown over each other. The NoC routers have up to two additional ports, one connecting to a router in the higher layer, and another connecting to a router in the lower layer. Router 111 in the middle layer of the example has both ports used, one connecting to the router at the top layer and another connecting to the router at the bottom layer. Routers 110 and 112 are at the bottom and top mesh layers respectively, therefore they have only the upper facing port 113 and the lower facing port 114 respectively connected.

Packets are message transport units for intercommunication between various components. Routing involves identifying a path composed of a set of routers and physical links of the network over which packets are sent from a source to a destination. Components are connected to one or multiple ports of one or multiple routers; with each such port having a unique ID. Packets carry the destination's router and port ID for use by the intermediate routers to route the packet to the destination component.

Examples of routing techniques include deterministic routing, which involves choosing the same path from A to B for every packet. This form of routing is independent from the state of the network and does not load balance across path diversities, which might exist in the underlying network. However, such deterministic routing may implemented in hardware, maintains packet ordering and may be rendered free of network level deadlocks. Shortest path routing may minimize the latency as such routing reduces the number of hops from the source to the destination. For this reason, the shortest path may also be the lowest power path for communication between the two components. Dimension-order routing is a form of deterministic shortest path routing in 2-D, 2.5-D, and 3-D mesh networks. In this routing scheme, messages are routed along each coordinates in a particular sequence until the message reaches the final destination. For example in a 3-D mesh network, one may first route along the X dimension until it reaches a router whose X-coordinate is equal to the X-coordinate of the destination router. Next, the message takes a turn and is routed in along Y dimension and finally takes another turn and moves along the Z dimension until the message reaches the final destination router. Dimension ordered routing may be minimal turn and shortest path routing.

FIG. 2(a) pictorially illustrates an example of XY routing in a two dimensional mesh. More specifically, FIG. 2(a) illustrates XY routing from node ‘34’ to node ‘00’. In the example of FIG. 2(a), each component is connected to only one port of one router. A packet is first routed over the x-axis till the packet reaches node ‘04’ where the x-coordinate of the node is the same as the x-coordinate of the destination node. The packet is next routed over the y-axis until the packet reaches the destination node.

In heterogeneous mesh topology in which one or more routers or one or more links are absent, dimension order routing may not be feasible between certain source and destination nodes, and alternative paths may have to be taken. The alternative paths may not be shortest or minimum turn.

Source routing and routing using tables are other routing options used in NoC. Adaptive routing can dynamically change the path taken between two points on the network based on the state of the network. This form of routing may be complex to analyze and implement.

A NoC interconnect may contain multiple physical networks. Over each physical network, there may exist multiple virtual networks, wherein different message types are transmitted over different virtual networks. In this case, at each physical link or channel, there are multiple virtual channels; each virtual channel may have dedicated buffers at both end points. In any given clock cycle, only one virtual channel can transmit data on the physical channel.

NoC interconnects may employ wormhole routing, wherein, a large message or packet is broken into small pieces known as flits (also referred to as flow control digits). The first flit is the header flit, which holds information about this packet's route and key message level info along with payload data and sets up the routing behavior for all subsequent flits associated with the message. Optionally, one or more body flits follows the head flit, containing the remaining payload of data. The final flit is the tail flit, which in addition to containing the last payload also performs some bookkeeping to close the connection for the message. In wormhole flow control, virtual channels are often implemented.

The physical channels are time sliced into a number of independent logical channels called virtual channels (VCs). VCs provide multiple independent paths to route packets, however they are time-multiplexed on the physical channels. A virtual channel holds the state needed to coordinate the handling of the flits of a packet over a channel. At a minimum, this state identifies the output channel of the current node for the next hop of the route and the state of the virtual channel (idle, waiting for resources, or active). The virtual channel may also include pointers to the flits of the packet that are buffered on the current node and the number of flit buffers available on the next node.

The term “wormhole” plays on the way messages are transmitted over the channels: the output port at the next router can be so short that received data can be translated in the head flit before the full message arrives. This allows the router to quickly set up the route upon arrival of the head flit and then opt out from the rest of the conversation. Since a message is transmitted flit by flit, the message may occupy several flit buffers along its path at different routers, creating a worm-like image.

Based upon the traffic between various end points, and the routes and physical networks that are used for various messages, different physical channels of the NoC interconnect may experience different levels of load and congestion. The capacity of various physical channels of a NoC interconnect is determined by the width of the channel (number of physical wires) and the clock frequency at which it is operating. Various channels of the NoC may operate at different clock frequencies, and various channels may have different widths based on the bandwidth requirement at the channel. The bandwidth requirement at a channel is determined by the flows that traverse over the channel and their bandwidth values. Flows traversing over various NoC channels are affected by the routes taken by various flows. In a mesh or Taurus NoC, there may exist multiple route paths of equal length or number of hops between any pair of source and destination nodes. For example, in FIG. 2(b), in addition to the standard XY route between nodes 34 and 00, there are additional routes available, such as YX route 203 or a multi-turn route 202 that makes more than one turn from source to destination.

In a NoC with statically allocated routes for various traffic slows, the load at various channels may be controlled by intelligently selecting the routes for various flows. When a large number of traffic flows and substantial path diversity is present, routes can be chosen such that the load on all NoC channels is balanced nearly uniformly, thus avoiding a single point of bottleneck. Once routed, the NoC channel widths can be determined based on the bandwidth demands of flows on the channels. Unfortunately, channel widths cannot be arbitrarily large due to physical hardware design restrictions, such as timing or wiring congestion. There may be a limit on the maximum channel width, thereby putting a limit on the maximum bandwidth of any single NoC channel.

Additionally, wider physical channels may not help in achieving higher bandwidth if messages are short. For example, if a packet is a single flit packet with a 64-bit width, then no matter how wide a channel is, the channel will only be able to carry 64 bits per cycle of data if all packets over the channel are similar. Thus, a channel width is also limited by the message size in the NoC. Due to these limitations on the maximum NoC channel width, a channel may not have enough bandwidth in spite of balancing the routes.

To address the above bandwidth concern, multiple parallel physical NoCs may be used. Each NoC may be called a layer, thus creating a multi-layer NoC architecture. Hosts inject a message on a NoC layer; the message is then routed to the destination on the NoC layer, where it is delivered from the NoC layer to the host. Thus, each layer operates more or less independently from each other, and interactions between layers may only occur during the injection and ejection times. FIG. 3(a) illustrates a two layer NoC. Here the two NoC layers are shown adjacent to each other on the left and right, with the hosts connected to the NoC replicated in both left and right diagrams. A host is connected to two routers in this example—a router in the first layer shown as R1, and a router is the second layer shown as R2. In this example, the multi-layer NoC is different from the 3D NoC, i.e. multiple layers are on a single silicon die and are used to meet the high bandwidth demands of the communication between hosts on the same silicon die. Messages do not go from one layer to another. For purposes of clarity, the present application will utilize such a horizontal left and right illustration for multi-layer NoC to differentiate from the 3D NoCs, which are illustrated by drawing the NoCs vertically over each other.

In FIG. 3(b), a host connected to a router from each layer, R1 and R2 respectively, is illustrated. Each router is connected to other routers in its layer using directional ports 301, and is connected to the host using injection and ejection ports 302. A bridge-logic 303, or bridge, may sit between the host and the two NoC layers to determine the NoC layer for an outgoing message and sends the message from host to the NoC layer, and also perform the arbitration and multiplexing between incoming messages from the two NoC layers and delivers them to the host.

In a multi-layer NoC, the number of layers needed may depend upon a number of factors such as the aggregate bandwidth requirement of all traffic flows in the system, the routes that are used by various flows, message size distribution, maximum channel width, etc. Once the number of NoC layers in NoC interconnect is determined in a design, different messages and traffic flows may be routed over different NoC layers. Additionally, one may design NoC interconnects such that different layers have different topologies in number of routers, channels and connectivity. The channels in different layers may have different widths based on the flows that traverse over the channel and their bandwidth requirements.

In a NoC interconnect, if the traffic profile is not uniform and there is a certain amount of heterogeneity (e.g., certain hosts talking to each other more frequently than the others), the interconnect performance may depend on the NoC topology and where various hosts are placed in the topology with respect to each other and to what routers they are connected to. For example, if two hosts talk to each other frequently and require higher bandwidth than other interconnects, then they should be placed next to each other. This will reduce the latency for this communication which thereby reduces the global average latency, as well as reduce the number of router nodes and links over which the higher bandwidth of this communication must be provisioned.

Moving two hosts closer together may make certain other hosts far apart since all hosts must fit into the 2D planar NoC topology without overlapping with each other. Thus, various tradeoffs must be made and the hosts must be placed after examining the pair-wise bandwidth and latency requirements between all hosts so that certain global cost and performance metrics is optimized. The cost and performance metrics can be, for example, average structural latency between all communicating hosts in number of router hops, or sum of bandwidth between all pair of hosts and the distance between them in number of hops, or some combination of these two. This optimization problem is known to be NP-hard and heuristic based approaches are often used. The hosts in a system may vary in shape and sizes with respect to each other, which puts additional complexity in placing them in a 2D planar NoC topology, packing them optimally while leaving little whitespaces, and avoiding overlapping hosts.

The optimization approaches introduced so far to determine the channel capacity, routes, host positions, etc., are useful when the exact traffic profile is known in advance at the NoC design time. If the precise traffic profile is not known at the design time, and the traffic profile changes during the NoC operation based on the SoC application's requirements, then the NoC design must allow these adjustments. For the NoC to allow these changes, the NoC must be designed so that it has knowledge of the changes that may occur in the traffic profile in a given system and ensure that any combination of allowable traffic profiles are supported by the NoC hardware architecture.

SUMMARY

In related art implementations, when a customer requests for a NoC to be generated, the customer may provide its own NoC specification, the performance requirements or performance functions, and the cost functions that the customer is interested in. The NoC may be generated by a design house and presented to the customer that meets their minimum performance requirements. However, in such implementations, the customer may determine that they are willing to incur more costs if performance can be improved by a particular margin (e.g. 10%), or they may determine that the cost is too high and want to determine if it is possible to generate a NoC that meets their performance requirements within a lower cost range. The design house thereby has to redesign and regenerate the NoC for the customer, which is a time and resource wasting process. There is a need for a method to present multiple NoCs that meet the minimum requirements as well as possible desired requirements, as well as a method for presenting to such customers possible generatable NoCs and the cost versus performance space of possible NoCs that may meet their absolute minimum and may also meet their margin requirements.

Aspects of the present disclosure include a method involving processing a NoC specification for a plurality of performance requirements of a NoC; generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements; for each of the plurality of NoCs, presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

Aspects of the present disclosure further include a non-transitory computer readable medium, storing instructions for executing a process. The instructions include processing a NoC specification for a plurality of performance requirements of a NoC; generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements; and for each of the plurality of NoCs, presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

Aspects of the present disclosure further include a method for generating a NoC, which can include processing a NoC specification for a plurality of performance requirements of a NoC; generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements; and for each of the plurality of NoCs, presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs, and selecting one of the plurality of NoCs for generation or manufacture.

Through such example implementations, multiple NoCs do not have to be repeatedly generated in response to customer feedback, thereby saving time and resources in generating a NoC. The customer can also view the performance versus cost gradient and can determine realistic NoCs that can be generated along the gradient or that exceed the gradient, and select the NoC for generation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a), 1(b) 1(c) and 1(d) illustrate examples of Bidirectional ring, 2D Mesh, 2D Taurus, and 3D Mesh NoC Topologies.

FIG. 2(a) illustrates an example of XY routing in a related art two dimensional mesh.

FIG. 2(b) illustrates three different routes between a source and destination nodes.

FIG. 3(a) illustrates an example of a related art two layer NoC interconnect.

FIG. 3(b) illustrates the related art bridge logic between host and multiple NoC layers.

FIG. 4 illustrates a 4×2 mesh NoC mapping three traffic profiles using XY routing.

FIG. 5 illustrates an example user display showing a range of possible generated NoCs over a metric, in accordance with an example implementation.

FIG. 6 illustrates an example flow diagram, in accordance with an example implementation.

FIG. 7 illustrates another example user display, in accordance with an example implementation.

FIG. 8 illustrates a computer/server block diagram upon which the example implementations described herein may be implemented.

DETAILED DESCRIPTION

The following detailed description provides further details of the figures and example implementations of the present application. Reference numerals and descriptions of redundant elements between figures are omitted for clarity. Terms used throughout the description are provided as examples and are not intended to be limiting. For example, the use of the term “automatic” may involve fully automatic or semi-automatic implementations involving user or administrator control over certain aspects of the implementation, depending on the desired implementation of one of ordinary skill in the art practicing implementations of the present application.

In example implementations, a NoC interconnect is generated from a specification by utilizing design tools. The specification can contain constraints such as bandwidth/Quality of Service (QoS)/latency attributes that is to be met by the NoC, and can be in various software formats depending on the design tools utilized. Once the NoC is generated through the use of design tools on the specification to meet the specification requirements, the physical architecture can be implemented either by manufacturing a chip layout to facilitate the NoC or by generation of a register transfer level (RTL) for execution on a chip to emulate the generated NoC, depending on the desired implementation. Specifications may be in common power format (CPF), Unified Power Format (UPF), or others according to the desired specification. Specifications can be in the form of traffic specifications indicating the traffic, bandwidth requirements, latency requirements, interconnections and so on depending on the desired implementation. Specifications can also be in the form of power specifications to define power domains, voltage domains, clock domains, and so on, depending on the desired implementation.

A distributed NoC interconnect connects various components in a system on chip with each other using multiple routers and point to point links between the routers. The traffic profile of a SoC includes the transactions between various components in the SoC and their properties (e.g., Quality of Service (QoS), priority, bandwidth and latency requirements, transaction sizes, etc.). The traffic profile information may be used to determine how various transactions will be routed in the NoC topology, and accordingly provision the link capacities, virtual channels and router nodes of the NoC. Accurate knowledge of the traffic profile can lead to an optimized NoC hardware with minimal overprovisioning in terms of link wires, virtual channel buffers and additional router nodes. A variety of SoCs today are designed to run a number of different applications; the resulting NoC traffic profile therefore may differ based on how and in what market segments the SoC is deployed, and what applications are supported. Supporting a variety of traffic profiles offers several challenges in the NoC design and optimization. Even if multiple traffic profiles are supported functionally, the traffic profile observed in a particular setting may be different from the set of profiles for which the NoC is optimized, leading to sub-optimal power consumption and NoC performance.

Example implementations described herein are directed to solutions for 2-D, 2.5-D and 3-D NoC interconnects. The example implementations may involve various aspects, such as: 1) designing a NoC to one or more traffic profiles of a traffic specification by mapping their transactions to NoC and allocating routes, virtual channels, and layers; 2) supporting hardware reconfigurability in the NoC to be able to optimize the NoC performance for a given subset of traffic profiles present in a SoC; 3) using example implementations herein to process each flow to optimize the mapping of the flows to the NoC hardware; 5) based on the determined flows, generating the reconfiguration information to be loaded into the NoC hardware; and 6) finally transmitting the reconfiguration information to the NoC in a format that can be loaded into NoC reconfiguration hardware.

Example implementations are directed to the utilization of machine learning based algorithms. In the related art, a wide range of machine learning based algorithms have been applied to image or pattern recognition, such as the recognition of obstacles or traffic signs of other cars, or the categorization of elements based on a specific training. In view of the advancement in power computations, machine learning has become more applicable for the generation of NoCs and for the mapping of traffic flows of NoCs.

In example implementations, the NoC is designed with agents, bridges, and the traffic specification, wherein a mapping algorithm attempts to map the traffic flows and determine if the flows should be included in the NoC generation process or not. Flows are processed in an incremental way. In example implementations, the specification is also processed to determine the characteristics of the NoC to be generated, the characteristics of the flow (e.g. number of hops, bandwidth requirements, type of flow such as request/response, etc.), flow mapping decision strategy (e.g., limit on number of new virtual channels to be constructed, using of existing VCs, yx/xy mapping, other routing types), and desired strategy to be used for how the flows are to be mapped to the network.

FIG. 4 illustrates an example of a traffic specification including multiple traffic profiles mapped to the NoC interconnect and mapping the transactions. Here there are three traffic profiles that need to be supported in a NoC interconnect connecting eight hosts, A, B, C, D, E, F, G, H. The inter-component communications of the three traffic profiles are as follows:

Traffic Profile 1: A<->B; A<->G;

Traffic Profile 2: A<->C; B<->D; D<->G; E<->F;

Traffic Profile 3: G<->C;

The example NoC of FIG. 4 is a 4×2 mesh topology. To support the three traffic profiles, routes and virtual channels are allocated for each transaction of all of the traffic profiles. In this case, a single NoC layer is allocated (for additional bandwidth and channels, more NoC layers may be allocated). A number of schemes can be used for allocation of NoC channels and routes and multiple layers, some of which are described in U.S. application Ser. Nos. 13/599,559, 13/745,684, and 13/752,226, hereby incorporated by reference for all purposes in their entirety. In this example, XY routes are used for all transactions, and the links and router nodes along the routes of all transactions in the three traffic profiles are allocated as shown in FIG. 4. Virtual channels allocated at various links between routers are omitted for clarity.

In related art implementations, one possible problem with the provided performance requirements is that, as such performance requirements may be provided by third parties or users, it may be uncertain as to whether a performance requirement is an absolute requirement or a desired requirement. In an example, a user incorporating a desired performance requirement in a NoC generation system may end up generating NoCs that have unacceptable costs, or lopsided costs when a significantly better NoC cost wise could have been generated in exchange for a slightly less restricted performance requirement. Thus, the generated NoCs may not meet the true requirements of the third parties or users.

Example implementations are directed to capturing input requirements and forming metrics that can be utilized to determine which of the possible generated NoCs can be further optimized. In example implementations, traffic flows are mapped, whereupon a NoC is selected and traffic flows are implemented with incremental refinement until the characteristics of the traffic flows are maximized.

FIG. 5 illustrates an example user display showing a range of possible generated NoCs over a metric, in accordance with an example implementation. In one metric example, the cost metrics can involve some cost function incorporating the area of the NoC and the power consumption, which can be plotted against performance metrics which involves another cost function involving latency, bandwidth and QoS. As illustrated in FIG. 5, an interface is provided which illustrates generated NoCs (represented as dots in the graph), and the performance as determined from a performance metric function, in comparison with the cost of the generated NoC as defined the cost function.

In example implementations as illustrated in FIG. 5, the band lines can indicate whether a certain requirement can tolerate something lower (margin) or if it is an absolute value that must be met (absolute). When presented with the possible generated NoCs, there is a performance divided by area slope, and a visualization that indicates the generated NoCs that meet the minimum versus being better than a desired margin. Example implementations are directed to facilitating the visualization and providing methods to capturing input requirements to facilitate flexibility in selecting the flows that are truly desired for a NoC. Through the provision of the slope, the NoC designer can thereby determine the tradeoffs between performance and cost over the desired performance and cost functions.

In example implementations, once such visualizations can be provided, NoC generation systems can be utilized to prioritize not only trading off one flow versus the other, but also prioritizing and potentially conducting multiple passes through the optimization process for refinement. For example, in a first pass, the generated NoCs can include all of the NoCs that can meet the absolute minimum requirements, which can then be further optimized to determine the desired extra margin and the costs associated with such optimizations. Such example implementations are in contrast to related art implementations which can only provide a single-stage process.

FIG. 6 illustrates an example flow, in accordance with an example implementation. At 600, a NoC specification and one or more parameters are processed. At 601, based on the processing of the NoC specification and the one or more parameters, the margin, absolute performance requirements and other limits (e.g. power limits, QoS requirement, bandwidth requirements, etc.) are determined. At 602, the weights for the performance function and the cost function are processed. At 603, the NoCs are generated and associated with values from the performance function and the cost function, whereupon the slope for the performance versus cost is determined across the generated NoCs. At 604, the slope and generated NoCs are provided as illustrated in FIG. 5.

In example implementations, the slope can be modified by a desired gradient and shifted according to the desired implementation. Such gradients can include a cost gradient and performance gradient that is shifted to reflect the desired cost to pay for the NoC generation or performance. In example implementations, the traffic specification can also indicate a desired margin and a cost gradient that the user is willing to pay to effect the desired margin.

In example implementations, additional modifiers can be provided for each traffic flow. For example, the input specification can include various flags to indicate a flow as latency sensitive or latency insensitive.

Such example implementations provide the ability to distinguish between the desired flows versus flows that are not as important, as well as determining that when a flow mapping algorithm is utilized, which flow mapping algorithms provide NoCs meeting the desired performance versus cost tradeoff. Once the visualization is provided, a customer can thereby generate the desired NoC from the plurality of NoCs determined by the machine learning algorithm, or can cause the machine learning algorithm to execute more generations within the desired absolute and desired margin space.

FIG. 7 illustrates an example 3D visualization interface, in accordance with an example implementation. In example implementations, the cost function can also be divided into the desired parameters. Example parameters can include power consumption and area consumption, although other parameters are possible depending on the desired implementation. Such visualizations can be useful, for example, when a flow is implemented with a wire to trade dynamic power for leakage power. In such an implementation, an area gradient and a power gradient may also be utilized to modify the slope for filtering out the possible generated NoCs to meet the desired requirements. In such example implementations, the performance tradeoff in comparison to area and power can thereby be provided.

In example implementations as described in FIG. 7, there can also be a global power budget for NoC generation. The interface can include a slider knob for applying gradients for global power budget available versus area, which can adjust preferences for power or area. Further, for a generated NoC, an interface can be provided so that power or area restrictions can be specified for particular traffic flows. In this way, performance can be compared to two or more cost functions.

Further, in example implementations, the performance function can be specified based on latency and bandwidth. The interface as described in FIG. 7 can include a visualization that splits performance into latency and bandwidth. In such example implementations, traffic flows can be granulized into different types. For example, traffic flows can be classified as central processing unit (CPU) type traffic where communications are latency sensitive and can be flagged as such. Another type of flow can include a graphics processing unit (GPU) type communication where bandwidth is more important than latency. Another type of flow can include the video display type of flows, where average throughput over a period of time is important. To reflect the type of information needed to facilitate such flows, parameters such as latency, latency variation, bandwidth, jitter and so on can be utilized in singular or in combination to provide the performance function, and then expanded in the interface as described in FIG. 7 should the designer prefer a particular parameter to be optimized.

FIG. 8 illustrates an example computer system 800 on which example implementations may be implemented. The computer system 800 includes a server 805 which may involve an I/O unit 835, storage 860, and a processor 810 operable to execute one or more units as known to one of skill in the art. The term “computer-readable medium” as used herein refers to any medium that participates in providing instructions to processor 810 for execution, which may come in the form of computer-readable storage mediums, such as, but not limited to optical disks, magnetic disks, read-only memories, random access memories, solid state devices and drives, or any other types of tangible media suitable for storing electronic information, or computer-readable signal mediums, which can include transitory media such as carrier waves. The I/O unit processes input from user interfaces 840 and operator interfaces 845 which may utilize input devices such as a keyboard, mouse, touch device, or verbal command.

The server 805 may also be connected to an external storage 850, which can contain removable storage such as a portable hard drive, optical media (CD or DVD), disk media or any other medium from which a computer can read executable code. The server may also be connected an output device 855, such as a display to output data and other information to a user, as well as request additional information from a user. The connections from the server 805 to the user interface 840, the operator interface 845, the external storage 850, and the output device 855 may via wireless protocols, such as the 802.11 standards, Bluetooth® or cellular protocols, or via physical transmission media, such as cables or fiber optics. The output device 855 may therefore further act as an input device for interacting with a user.

The processor 810 may execute one or more modules. The NoC compiler 811 is configured to generate NoCs in the form of a layout or an RTL. The Machine learning Trainer 812 can be configured to train a machine learning algorithm to select a generated NoC for construction based on a performance/cost tradeoff. The performance visualizer 813 can be configured to provide visualizations as shown, for example, in FIG. 5 and FIG. 7.

Processor 810 can be configured to process a NoC specification for a plurality of performance requirements of a NoC; generate a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements; for each of the plurality of NoCs, present a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs as illustrated in FIG. 5 and FIG. 7. Upon receiving a selection, processor 810 can generate the NoC from the plurality of NoCs for the customer. The plurality of performance requirements can involve bandwidth requirements and latency requirements for a plurality of sets of traffic of the NoC specification. The plurality of performance requirements can involve performance requirements of selected one or more subsets of traffic of the NoC specification. The plurality of performance requirements can also involve multiple SoC/NoC use profiles. Further, the one or more costs comprises at least one of area, power consumption, and wiring congestion.

The presenting the difference and the one or more costs comprises providing a visualization for the plurality of NoCs based on a function incorporating performance and cost as illustrated in FIGS. 5 and 7. As illustrated in FIGS. 5 and 7, the function can be a gradient of performance and the one or more costs. The presenting the difference can involve providing a graphical display (e.g. scatterplot, histogram) comparing performance versus the one or more costs.

In addition, processors 810 can utilize machine learning algorithms configured to generate the NoCs based on the specified performance and cost/area functions. The machine learning based algorithm can also be configured to select a NoC from the plurality of NoCs for generation based on performance versus the one or more costs for the customer. Such machine learning based algorithms can be configured to select a NoC based on a computation of a gradient between the performance and the costs, and another function for NoCs having the same gradient.

Furthermore, some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations within a computer. These algorithmic descriptions and symbolic representations are the means used by those skilled in the data processing arts to most effectively convey the essence of their innovations to others skilled in the art. An algorithm is a series of defined steps leading to a desired end state or result. In the example implementations, the steps carried out require physical manipulations of tangible quantities for achieving a tangible result.

Moreover, other implementations of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the example implementations disclosed herein. Various aspects and/or components of the described example implementations may be used singly or in any combination. It is intended that the specification and examples be considered as examples, with a true scope and spirit of the application being indicated by the following claims. 

What is claimed is:
 1. A method for manufacturing a Network on Chip (NoC), comprising: processing a NoC specification for a plurality of performance requirements of a NoC; generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements; for each of the plurality of NoCs, presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs; selecting one of the plurality of NoCs for manufacture; and manufacturing the selected one of the plurality of NoCs.
 2. The method of claim 1, wherein the plurality of performance requirements comprises bandwidth requirements and latency requirements for a plurality of sets of traffic of the NoC specification.
 3. The method of claim 1, wherein the plurality of performance requirements comprises performance requirements of selected one or more subsets of traffic of the NoC specification.
 4. The method of claim 1, wherein the plurality of performance requirements comprises multiple SoC/NoC use profiles.
 5. The method of claim 1, wherein the one or more costs comprises at least one of area, power consumption, and wiring congestion.
 6. The method of claim 1, wherein the presenting the difference and the one or more costs comprises providing a visualization for the plurality of NoCs based on a function incorporating performance and cost.
 7. The method of claim 6, wherein the function is a gradient of performance and the one or more costs.
 8. The method of claim 1, further comprising utilizing a machine learning based method configured to select a NoC from the plurality of NoCs for generation based on performance versus the one or more costs.
 9. The method of claim 1, wherein the machine learning based method is configured to select a NoC based on a computation of a gradient between the performance and the costs, and another function for NoCs having the same gradient.
 10. The method of claim 1, wherein the presenting the difference comprises providing a graphical display comparing performance versus the one or more costs. 